MANIFEST.in
README.md
setup.py
pythondata_cpu_vexriscv/__init__.py
pythondata_cpu_vexriscv.egg-info/PKG-INFO
pythondata_cpu_vexriscv.egg-info/SOURCES.txt
pythondata_cpu_vexriscv.egg-info/dependency_links.txt
pythondata_cpu_vexriscv.egg-info/not-zip-safe
pythondata_cpu_vexriscv.egg-info/top_level.txt
pythondata_cpu_vexriscv/verilog/.gitignore
pythondata_cpu_vexriscv/verilog/.gitmodules
pythondata_cpu_vexriscv/verilog/Makefile
pythondata_cpu_vexriscv/verilog/README.md
pythondata_cpu_vexriscv/verilog/VexRiscv.v
pythondata_cpu_vexriscv/verilog/VexRiscv.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Full.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v
pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Min.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.yaml
pythondata_cpu_vexriscv/verilog/build.sbt
pythondata_cpu_vexriscv/verilog/project/build.properties
pythondata_cpu_vexriscv/verilog/project/plugins.sbt
pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala