LICENSE
MANIFEST.in
README.md
setup.py
pythondata_cpu_serv/__init__.py
pythondata_cpu_serv.egg-info/PKG-INFO
pythondata_cpu_serv.egg-info/SOURCES.txt
pythondata_cpu_serv.egg-info/dependency_links.txt
pythondata_cpu_serv.egg-info/not-zip-safe
pythondata_cpu_serv.egg-info/top_level.txt
pythondata_cpu_serv/verilog/.gitmodules
pythondata_cpu_serv/verilog/LICENSE
pythondata_cpu_serv/verilog/README.md
pythondata_cpu_serv/verilog/serv.core
pythondata_cpu_serv/verilog/servant.core
pythondata_cpu_serv/verilog/serving.core
pythondata_cpu_serv/verilog/west.yml
pythondata_cpu_serv/verilog/.github/workflows/ci.yml
pythondata_cpu_serv/verilog/.github/workflows/lint.yml
pythondata_cpu_serv/verilog/.github/workflows/openlane.yml
pythondata_cpu_serv/verilog/.github/workflows/pages.yml
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pythondata_cpu_serv/verilog/data/pipistrello.ucf
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pythondata_cpu_serv/verilog/data/ulx3s.lpf
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pythondata_cpu_serv/verilog/data/chameleon96/pinmap.tcl
pythondata_cpu_serv/verilog/doc/.nojekyll
pythondata_cpu_serv/verilog/doc/Makefile
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pythondata_cpu_serv/verilog/doc/index.rst
pythondata_cpu_serv/verilog/doc/interface.rst
pythondata_cpu_serv/verilog/doc/life_cycle.png
pythondata_cpu_serv/verilog/doc/make.bat
pythondata_cpu_serv/verilog/doc/modules.rst
pythondata_cpu_serv/verilog/doc/requirements.txt
pythondata_cpu_serv/verilog/doc/serv_alu.png
pythondata_cpu_serv/verilog/doc/serv_alu_int.png
pythondata_cpu_serv/verilog/doc/serv_bufreg.png
pythondata_cpu_serv/verilog/doc/serv_bufreg2.png
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pythondata_cpu_serv/verilog/doc/serv_bufreg_int.png
pythondata_cpu_serv/verilog/doc/serv_csr.png
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pythondata_cpu_serv/verilog/doc/serv_ctrl.png
pythondata_cpu_serv/verilog/doc/serv_ctrl_int.png
pythondata_cpu_serv/verilog/doc/serv_dataflow.png
pythondata_cpu_serv/verilog/doc/serv_decode.png
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pythondata_cpu_serv/verilog/doc/serv_rf_top.png
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pythondata_cpu_serv/verilog/rtl/serv_alu.v
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pythondata_cpu_serv/verilog/rtl/serv_csr.v
pythondata_cpu_serv/verilog/rtl/serv_ctrl.v
pythondata_cpu_serv/verilog/rtl/serv_decode.v
pythondata_cpu_serv/verilog/rtl/serv_immdec.v
pythondata_cpu_serv/verilog/rtl/serv_mem_if.v
pythondata_cpu_serv/verilog/rtl/serv_rf_if.v
pythondata_cpu_serv/verilog/rtl/serv_rf_ram.v
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pythondata_cpu_serv/verilog/rtl/serv_rf_top.v
pythondata_cpu_serv/verilog/rtl/serv_state.v
pythondata_cpu_serv/verilog/rtl/serv_synth_wrapper.v
pythondata_cpu_serv/verilog/rtl/serv_top.v
pythondata_cpu_serv/verilog/servant/ecppll.v
pythondata_cpu_serv/verilog/servant/ice40_pll.v
pythondata_cpu_serv/verilog/servant/servant.v
pythondata_cpu_serv/verilog/servant/servant_ac701.v
pythondata_cpu_serv/verilog/servant/servant_arbiter.v
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pythondata_cpu_serv/verilog/servant/servant_lx9.v
pythondata_cpu_serv/verilog/servant/servant_lx9_clock_gen.v
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pythondata_cpu_serv/verilog/servant/servant_ram.v
pythondata_cpu_serv/verilog/servant/servant_ram_quartus.sv
pythondata_cpu_serv/verilog/servant/servant_timer.v
pythondata_cpu_serv/verilog/servant/servant_upduino2.v
pythondata_cpu_serv/verilog/servant/servclone10.v
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pythondata_cpu_serv/verilog/servant/service.v
pythondata_cpu_serv/verilog/servant/service_go_board.v
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pythondata_cpu_serv/verilog/zephyr/drivers/Kconfig
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pythondata_cpu_serv/verilog/zephyr/drivers/serial/Kconfig
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pythondata_cpu_serv/verilog/zephyr/drivers/timer/CMakeLists.txt
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